Semiconductor device having a high withstand voltage

ABSTRACT

To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region  111  and gate electrode  106 , having N+ emitter region  104  and P+ emitter region  100 , and controlling conduction between emitter and collector by voltage applied to gate electrode  106 , the shape of contact opening  108  contacting emitter (N+ emitter region  104  and P+ emitter region  100 ) and emitter electrode is formed of curved lines at four corners. Hence, eliminating right-angle apex, hole current from the field region into the emitter electrode after switching off is prevented from concentrating at one point.

This is a 371 national phase application of PCT/JP2004/008516 filed 10Jun. 2004, claiming priority to Japanese Patent Application No.2003-195498 filed 11 Jul. 2003, the contents of which are incorporatedherein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor device of highwithstand voltage suited to switching of large current. Moreparticularly, it relates to a semiconductor device intended to preventoverheating when switching off.

BACKGROUND ART

As conventional semiconductor devices, insulated gate semiconductordevices disclosed in patent references 1 and 2 are known. In theseinsulated gate semiconductor devices, by applying a gate voltage to aninsulated gate, a field effect is produced in a channel region in asemiconductor substrate, and current flows between emitter andcollector. Accordingly, a contact opening is provided in order toexchange carriers between an emitter region and an emitter electrode. Atypical example of this kind of insulated gate semiconductor device hasa structure as shown in FIG. 18 to FIG. 20. FIG. 18 and FIG. 20 arelongitudinal sectional views, and FIG. 19 is a plan sectional view oflevel A-A in these drawings. FIG. 18 is a sectional view of position B-Bin FIG. 19 and FIG. 20. FIG. 20 is a sectional view of position C-C inFIG. 18 and FIG. 19.

In the insulated gate semiconductor device shown in FIG. 18 to FIG. 20,on the principal plane of level A-A side of semiconductor substrate, N+emitter region 904 and P+ emitter region 900 are provided. Contactingwith the lower part of them, P body region 903 is disposed. Furtherbeneath the P body region 903, N drift region 902 is provided, and P+collector region 901 is provided furthermore beneath. So far is within asemiconductor substrate (in this specification, the entire semiconductorsingle crystal of a start wafer and a layer formed by epitaxial growthon its surface is called a semiconductor substrate). In thesemiconductor substrate, still more, P field regions 911 for dividingindividual devices are formed from the level A-A side. Bottoms of the Pfield regions 911 reach into the N drift region 902.

Part of the semiconductor substrate is dug in from the level A-A side,and gate electrodes 906 are provided in the cavity. Gate electrodes 906are insulated from the regions within the semiconductor substrate bygate insulating films 905. Above the semiconductor substrate, emitterelectrode 909 and gate wirings 916 are provided. The emitter electrode909 is an electrode conducting to N+ emitter region 904 and P+ emitterregion 900 within a range of contact opening 908. The gate wiring 916conducts with gate electrodes 906 in other position than shown. Gateelectrodes 906 and gate wiring 916 are insulated from other parts byinterlayer insulating film 907. Beneath the semiconductor substrate,collector electrode 910 is provided.

In this structure, when a power voltage is applied between the emitterelectrode 909 and collector electrode 910, by on/off switching of gatevoltage to gate electrodes 906, current between the emitter electrode909 and the collector electrode 910 can be switched. Herein, contactopening 908 which is a contact region between the emitter region (N+emitter region 904 and P+ emitter region 900) and emitter electrode 909is formed in a rectangular shape in FIG. 19. This is intended toincrease the area of the contact opening 908 and heighten the latch-upresistance while avoiding short-circuiting to gate electrodes 906 andgate wirings 916.

Patent reference 1, Japanese Patent Publication No. H6-101565

Patent reference 2, Japanese Laid-open Patent No. H10-229191

Such conventional semiconductor device, however, had a problem of localheating after switching off. The cause lies in the shape of the contactopening 908. That is, after switching off, as indicated by arrow I inFIG. 21, hole current from P field region 911 flows into the emitterelectrode 909. As shown in FIG. 22, this hole current density is high atfour corners of the rectangular contact opening 908. There is no contactopening 908 in a region between devices, and holes in the P field region911 are directed toward the nearest contact opening 908. As a result,when interrupting a large current, in particular, the device may bedestructed due to excessive heat generation. This phenomenon isprominent at corners of terminal end of device array.

As means for lessening concentration of current, simply, it may beconsidered to increase the area of contact opening 908. But it islimited in relation to insulation from gate electrodes 906 and others.If the contact opening 908 is excessively increased in area, holes maypass through the emitter electrode 909 too much in ON state. As aresult, ON voltage becomes higher. It is hence difficult to increase thearea of the contact opening 908.

The present invention is devised to solve these problems of theconventional semiconductor device. It is hence an object thereof topresent a semiconductor device capable of stable operation of largecurrent by lessening current concentration at corners of contact openingafter switching off and suppressing local heat generation, withoutheightening ON voltage.

DISCLOSURE OF THE INVENTION

The semiconductor device of the present invention devised to solve theproblems comprises an active device provided in a semiconductorsubstrate facing its principal plane, and a contact electrode providedoutside of the semiconductor substrate conducting with the activedevice. It is a feature (1) herein that a marginal corner of conductingportion of the active device and the contact electrode is formed with acurved line or with an obtuse angle.

In this semiconductor device, when the active device is switched off,residual carriers in the active device escape to the contact electrode.This current escaping route is limited to the conducting portion of theactive device and the contact electrode. Herein, since the marginalcorner of the conducting portion is formed with a curved line or with anobtuse angle, the current of the conducting portion into the corner isdispersed somewhat. Hence, current density is not excessively high atthe apex of edge. Hence, damage by heat generation is small. On theother hand, the ON voltage is not particularly high. This is becausearea of the conducting portion is not increased. Hence, carriers do notpass too much into the contact electrode in ON state.

The semiconductor device of the present invention may have, instead ofthe feature (1) above, a feature (2) of the shape of conducting portionof the active device and contact electrode formed in a broader width inan end portion than in the central portion. As a result, currentconcentration in the end portion of conducting portion is lessened. Thisis because area of the end portion is slightly wider. On the other hand,area of the entire conducting portion is not so much wider. This isbecause width is not large in the central area. Accordingly, preventionof local heat generation after switching off and low ON voltage in ONstate are realized.

Further, the semiconductor device of the invention may have, instead ofthe feature (1) or (2), a feature (3) that impurity concentration islower at an end portion of conducting portion of the active device andthe contact electrode than in the central portion of it. As a result,current concentration at the end portion of conducting portion islessened. This is because the end portion with lower impurityconcentration has a higher resistance, so that current is more likely toflow into the central portion with lower resistance. On the other hand,area is not increased in the entire conducting portion. To the contrary,since the end portion has a higher resistance, the entire conductingportion has a slightly increased resistance. Therefore, local heatgeneration after switching off is prevented, while the ON voltage in ONstate is low.

Generally, in this kind of semiconductor device, a plurality of activedevices are discretely arranged in a semiconductor substrate, and eachactive device has a conducting portion to a contact electrode. In suchconfiguration, it is not necessary that one of the features of (1) to(3) is realized in contacting portions of all active devices. It issufficient that a feature is realized in contacting portions of some ofthe active devices. In such a case, it is particularly beneficial torealize one of the features (1) to (3) in the conducting portions of theactive devices located at ends. This is because current from peripheralregions of the semiconductor substrate is also concentrated in theconductive portions of active devices located at ends. Therefore, ascompared with active devices located in central area, the situation isseverer as for current concentration after switching off. Thisphenomenon is particularly notable in the corner portion or end portionat the opposite side to other active devices. This is because distancefrom the peripheral region is very close for such corner portions.

The invention is particularly significant when applied in an insulatedgate field-effect semiconductor device comprising an insulated gateinsulated from an active device, and a field semiconductor regionbetween active devices, for switching an active device by a voltageapplied to the insulated gate. In such semiconductor device, generally,the field semiconductor region does not contact directly with thecontact electrode. The position immediately above the fieldsemiconductor region is usually an area for wiring to an insulated gate,and it is required to be insulated there from. Accordingly, afterswitching off, residual carriers in the field semiconductor regioncannot directly escape to the contact electrode. Hence, by way of thenearest active device, they escape via its conducting portion to thecontact electrode. As a result, current density is likely to be high inthe marginal space of the conducting portion, in particular, in cornerportion. By applying one of the features (1) to (3) in this area, damageby current concentration can be lessened. Generally, the fieldsemiconductor region is low in impurity concentration, in the case offeature (3), at the end portion of the conducting portion, the fieldsemiconductor region and contact electrode should directly contact witheach other.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view (B-B in FIG. 2) showing a structure ofinsulated gate field-effect semiconductor device in a first embodiment.

FIG. 2 is a sectional view (A-A in FIG. 1) showing the structure ofinsulated gate field-effect semiconductor device in the firstembodiment.

FIG. 3 is a sectional view (D-D in FIG. 1) showing the structure ofinsulated gate field-effect semiconductor device in the firstembodiment.

FIG. 4 is a sectional view (C-C in FIG. 1) showing the structure ofinsulated gate field-effect semiconductor device in the firstembodiment.

FIG. 5 is a conceptual diagram showing distribution of hole currentafter switching off of insulated gate field-effect semiconductor devicein the first embodiment.

FIG. 6 is a diagram showing variation of plane shape of contact openingin the first embodiment.

FIG. 7 is a diagram showing variation of a measure applied only in theedge of terminal end of device array in the first embodiment.

FIG. 8 is a sectional view (part 1, section B-B) showing a manufacturingprocess of insulated gate field-effect semiconductor device in the firstembodiment.

FIG. 9 is a sectional view (part 2, section B-B) showing a manufacturingprocess of insulated gate field-effect semiconductor device in the firstembodiment.

FIG. 10 is a sectional view (part 3, section C-C) showing amanufacturing process of insulated gate field-effect semiconductordevice in the first embodiment.

FIG. 11 is a sectional view (part 4, section C-C) showing amanufacturing process of insulated gate field-effect semiconductordevice in the first embodiment.

FIG. 12 is a sectional view (part 5, section B-B) showing amanufacturing process of insulated gate field-effect semiconductordevice in the first embodiment.

FIG. 13 is a sectional view (C-C in FIG. 14) showing a structure ofinsulated gate field-effect semiconductor device in a second embodiment.

FIG. 14 is a sectional view (A-A in FIG. 13) showing a structure ofinsulated gate field-effect semiconductor device in the secondembodiment.

FIG. 15 is a diagram showing variation of plane shape of contact openingin the first embodiment.

FIG. 16 is a sectional view (A-A in FIG. 17) showing a structure ofinsulated gate field-effect semiconductor device in a third embodiment.

FIG. 17 is a sectional view (C-C in FIG. 16) showing a structure ofinsulated gate field-effect semiconductor device in the thirdembodiment.

FIG. 18 is a section B-B view showing a structure of insulated gatefield-effect semiconductor device in the prior art.

FIG. 19 is a section A-A view showing a structure of insulated gatefield-effect semiconductor device in the prior art.

FIG. 20 is a section C-C view showing a structure of insulated gatefield-effect semiconductor device in the prior art.

FIG. 21 is a conceptual diagram (part 1, section B-B) showingdistribution of hole current after switching off of insulated gatefield-effect semiconductor device in the prior art.

FIG. 22 is a conceptual diagram (part 2, section A-A) showingdistribution of hole current after switching off of insulated gatefield-effect semiconductor device in the prior art.

FIG. 23 is a conceptual diagram (part 3, section B-B at an end portion)showing distribution of hole current after switching off of insulatedgate field-effect semiconductor device in the prior art.

BEST MODE FOR CARRYING OUT THE INVENTION

Exemplary embodiments of the invention are specifically described belowwhile referring to the accompanying drawings. In the followingembodiments, the present invention is applied to an insulated gatefield-effect semiconductor device used in switching of a large current.

First Embodiment

A structure of an insulated gate field-effect semiconductor deviceaccording to a first embodiment is described by referring to FIG. 1 toFIG. 4. FIG. 1, FIG. 3, and FIG. 4 are longitudinal sectional views, andFIG. 2 is a plan sectional view at level A-A in these drawings. FIG. 1is a sectional view of position B-B in FIG. 2 to FIG. 4. FIG. 3 is asectional view of position D-D in FIG. 1 and FIG. 2. FIG. 4 is asectional view of position C-C in FIG. 1 and FIG. 3.

In the insulated gate semiconductor device shown in FIG. 1 to FIG. 4, onthe principal plane of level A-A side of semiconductor substrate, N+emitter region 104 of high impurity concentration and P+ emitter region100 of high impurity concentration are provided. Contacting with thelower part of them, P body region 103 is disposed. Further beneath the Pbody region 103, N drift region 102 is provided, and P+ collector region101 is provided furthermore beneath. So far is within a semiconductorsubstrate. In the semiconductor substrate, still more, P field regions111 for dividing individual devices are formed from the level A-A side.The bottom of the P field region 111 reaches into the N drift region102. Impurity concentration of P field region 111 is lower than impurityconcentration of P+ emitter region 100.

Part of the semiconductor substrate is dug in from the level A-A side,and gate electrodes 106 of trench structure are formed in the cavity.Gate electrodes 106 are insulated from the regions within thesemiconductor substrate by gate insulating films 105. The shape withinthe plane of a gate electrode 106 is long in the lateral direction inFIG. 2, and multiple gate electrodes 106 are formed parallel and atequal intervals. Bottom of gate electrodes 106 is deeper than the bottomof the P body region 103, but is shallower than the bottom of the Pfield region 111. That is, the structure of the semiconductor device isschematically described as follows. By the trench structure of gateelectrodes 106, the level A-A side of the semiconductor substrate isdivided like ridges, and each ridge is divided into multiple cells bythe P field region 111. Each cell composes an insulated gate transistorhaving an emitter (N+ emitter region 104 and P+ emitter region 100) andbody (P body region 103). On the whole, the semiconductor device has amultiplicity of insulated gate transistors disposed discretely.

Above the level A-A side principal plane of the semiconductor substrate,emitter electrode 109 and gate wirings 116 are provided. The emitterelectrode 109 contacts with the emitter (N+ emitter region 104 and P+emitter region 100) in each cell. The contacting portion is a contactopening 108. As clear from FIG. 2, in the contact opening 108, both N+emitter region 104 and P+ emitter region 100 contact with the emitterelectrode 109. More specifically, the portions at both ends in thelateral direction in FIG. 2 in the contact opening 108 are occupied bythe P+ emitter regions 100. On the other hand, the N+ emitter regions104 are present in the central part in the lateral direction. Betweencontact opening 108 and contact opening 108, that is, in the position(see FIG. 1) under the gate wiring 116, in part, the P field region 111has reached the level A-A of the semiconductor substrate.

The gate wiring 116 is connected to gate electrodes 106 in otherposition than shown. As a result, a voltage can be applied to gateelectrodes 106. Gate electrodes 106 and gate wiring 116 are insulatedfrom other parts by an interlayer insulating film 107. A collectorelectrode 110 is provided on the surface at the side of the P+ collectorregion 101 of the semiconductor substrate. A power voltage is appliedbetween the emitter electrode 109 and collector electrode 110. In thisstructure, whether gate voltage is applied or not to gate electrodes106, current between the emitter electrode 109 and the collectorelectrode 110 can be controlled by on/off switching.

In the insulated gate transistor of the embodiment, as shown in FIG. 2,a feature lies in the plane shape of the contact opening 108. That is,while it was rectangular in the prior art (see FIG. 19), but in theembodiment edges at four corners are formed in curved lines. As aresult, right-angle apexes are eliminated.

The insulated gate transistor of the embodiment operates as follows.That is, the insulated gate transistor of the embodiment is used in astate of a power voltage applied between the emitter electrode 109 andthe collector electrode 110. In this state, however, current does notflow between the emitter electrode 109 and the collector electrode 110.This is because the PN junction between the P body region 103 and Ndrift region 102 is biased inversely. That is, this is an OFF state.When a gate voltage is applied to gate electrodes 106, N channels areformed by field effect on faces facing to gate electrodes 106 in P bodyregions 103. As a result, an electron conducting route is connected fromN emitter region 104 to N channel formed in P body region 103, and to Ndrift region 102, and current flows between the emitter electrode 109and the collector electrode 110. This is an ON state. When the gatevoltage is cut off, it goes back to OFF state again.

In ON state, holes flow into a P field region 111 from N drift regions102 etc. As a result, the P field regions 111 is considerably high inhole concentration. When being switched off, holes accumulated in the Pfield region 111 are moved to escape to the emitter electrode 109.However, the P field region 111 does not contact directly with theemitter electrode 109. Accordingly, hole current from the P field region111 escapes via the contact opening 108 to the emitter electrode 109 byway of the P+ emitter region 100.

In the gate insulated transistor of the embodiment, the plane shape ofthe contact opening 108 brings about following merits. That is, there islittle harm by concentration of hole current at corners of the contactopening 108. The reason is that the corners are formed with curvedlines. In other words, since there is no right-angle apex at corners,hole current from the P field region 111 is dispersed in the entirecurved line portions at corners as shown in FIG. 5. Therefore, even atthe location of highest current density, the current density is lower ascompared with that at corner apex in the conventional insulated gatetransistor (see FIG. 22). Hence, excessive heat generation is not causedafter switching off.

In addition, area of the contact opening 108 is not larger as comparedwith the rectangular contact opening 908 in FIG. 19. It is rathersmaller. Hence, in ON state, holes do not escape to the emitterelectrode 109 excessively. Therefore, carrier concentration in thedevice is kept high in ON state. As a result, ON voltage is low.

Incidentally, in the gate insulated transistor of the embodiment, theshape of the contact opening 108 may be also formed by obtuse angles andstraight lines at four corners as shown in FIG. 6. In such shape, ascompared with the rectangular contact opening 908 in FIG. 19,concentration of current at corner apex is lessened. Further, the shapeof the contact opening 108 may be formed by merely rounding the fourcorners of a rectangle. Such measure is not required in all four cornersof the contact opening 108. For example, as shown in FIG. 7, if suchmeasure is taken only at corners of terminal ends of the device array, acertain effect is expected. This is because, as explained in the priorart in FIG. 23, current concentration is likely to occur at corners ofterminal ends of the device array.

Manufacturing process of gate insulated transistor of the embodiment isdescribed by referring to FIG. 8 to FIG. 12. In manufacture of gateinsulated transistor of the embodiment, a P+ silicon wafer is a startsubstrate. P+ silicon of this wafer becomes a P+ collector region 101.On its surface, an N type silicon layer is formed by epitaxial growth.This N type silicon layer becomes an N drift region 102. Entire singlecrystal silicon of the silicon wafer and a layer by epitaxial growth onit is called a semiconductor substrate in the present invention.Alternatively, an N silicon wafer may be used as a start substrate. Inthis case, the N silicon of the wafer is an N drift region 102. Byintroducing a P impurity from the back side surface, or by depositing aP silicon layer on the back side surface, a P+ collector region 101 canbe formed.

Successively, on the surface of the N silicon layer, a thermal oxidefilm of 500 nm in thickness is formed. This thermal oxide film ispatterned by photolithography and etching. As a result, the thermaloxide film is removed only in the portion for forming a P field region111. By ion implantation, boron is injected at acceleration voltage of60 keV. This ion implantation is a process for forming a P field region111. Dose should be large enough to invert the N silicon layer in thisrange (N drift region 102) into the P type. By subsequent thermaldiffusion, a P field region 111 is formed. The bottom depth of the Pfield region 111 is about 7 μm. Only in the device region but in theperipheral region, the oxide film is removed by wet etching by usinghydrofluoric acid. By heating and oxidizing again, an oxide film 107 b(see FIG. 8) of 50 nm in thickness is formed on the surface. At thisstage, by ion implantation again, boron is injected at accelerationvoltage of 60 keV. This ion implantation is a process for forming a Pbody region 103. Dose should be large enough to invert the N siliconlayer in this range (N drift region 102) into the P type. By subsequentthermal diffusion, a P body region 103 is formed. The bottom depth ofthe P body region 103 is about 5 μm. A section B-B view at this stage isFIG. 8.

On the oxide film 107 b, an oxide film 107 c is further deposited by CVDprocess (see FIG. 9, FIG. 10). Its thickness is 400 nm. The oxide films107 b and 107 c are patterned by etching. The pattern to be formed isthe pattern having openings in areas for forming gate electrodes 106. Inthis state, by dry etching of silicon, a trench opening 117 is formed.FIG. 9 is a section B-B view and FIG. 10 is a section C-C view at thisstage.

Only in the device region but in the peripheral region, the oxide films107 b and 107 c are removed by wet etching by using hydrofluoric acid.After that, by heating and oxidizing the surface of the semiconductor, agate insulating film 105 (thickness 100 nm) is formed. After formingpolycrystal silicon by CVD process, phosphorus is diffused to turn thepolycrystal into N+ type. Of the formed N+ polycrystal silicon, theportion filling trench opening 117 is a gate electrode 106. The N+polycrystal silicon on the surface of the semiconductor substrate isetched. That is, leaving the portion necessary for connection of gateelectrodes 106 and gate wiring 116, the N+ polycrystal silicon on thesurface is removed. FIG. 11 is a section C-C view at this stage.

Further, P+ emitter region 100 and N+ emitter region 104 are formedsequentially. These are formed by ion implantation and diffusion,respectively. Of course, proper pattern masks are used for ionimplantations. After removing all pattern masks, an interlayerinsulating film 107 (thickness 700 nm) is formed by CVD process. Apattern mask is formed on the interlayer insulating film 107, and theinterlayer insulating film 107 is processed by dry etching, and acontact opening 108 is opened. FIG. 12 is a section B-B view at thisstage. That is, the plane shape of the contact opening 108 is determinedby the pattern mask used in processing of the interlayer insulating film107. Then, by sputtering method, aluminium or other metal film is formedon the semiconductor substrate. By pattern etching of the film, anemitter electrode 109, a gate wiring 116, and other wirings are formed.At the back side, a collector electrode 110 is formed by sputteringmethod. Thus, the semiconductor device shown in FIG. 1 to FIG. 4 isfabricated.

Second Embodiment

A structure of an insulated gate field-effect semiconductor deviceaccording to a second embodiment is described by referring to FIG. 13and FIG. 14. FIG. 13 is a longitudinal sectional view, and a planesectional view at level A-A thereof is FIG. 14. FIG. 13 is a sectionalview of position C-C in FIG. 14. A sectional view of position B-B inFIG. 13 and FIG. 14 is same as FIG. 1 relating to the first embodimentexcept that the reference numerals 1** are changed to 2**. A sectionalview of position D-D in FIG. 14 is same as FIG. 3 relating to the firstembodiment except that the reference numerals are changed similarly. Inthe following explanation of the embodiment, when referring to FIG. 1and FIG. 3, it is supposed that the reference numerals are changed insuch manner.

In the insulated gate field-effect semiconductor device of theembodiment, what differs from the insulated gate field-effectsemiconductor device of the first embodiment lies only in the planeshape of the contact opening 208. All other parts are common with theinsulated gate field-effect semiconductor device in the firstembodiment. The common points are quoted from the description of thefirst embodiment, and only the different point is explained.

The contact opening 208 in the insulated gate field-effect semiconductordevice of this embodiment is basically a rectangular shape as shown inFIG. 14, with the width (vertical direction in FIG. 14) broader in theboth end portions (position C-C) than in the central portion (positionD-D). By defining in such shape, too, same as in the first embodiment,there is an advantage that harm by concentration of hole current afterswitching off is less. This is because the hole current from the P fieldregion 211 to the emitter electrode 209 after switching off flows in theboth end portions of the contact opening 208. Since this area isexpanded in this embodiment, peak value of local current density islower than in the prior art.

Area of the contact opening 208 is wider only slightly as compared withthe rectangular contact opening 908 (FIG. 19) in the prior art. This isbecause the width is expanded only in both end portions. Accordingly, inON state, holes do not escape to the emitter electrode 109 too much.Hence, the ON voltage is low.

In the insulated gate transistor of the embodiment, the shape of thecontact opening 208 may be formed of curved lines at four corners asshown in FIG. 15. In this variation, the feature of this embodiment andthe feature of the first embodiment are both realized. Therefore,current concentration is lessened more favorably. Of course, same as inthe first embodiment, the four corners may be formed by obtuse anglesand straight lines, or the four corners may be formed by merelyrounding. Even if such measure is taken only at terminal ends of thedevice array, a certain effect is expected.

Manufacturing process of insulated gate transistor of the embodiment issimilar to manufacturing process of insulated gate transistor of thefirst embodiment except that only the mask pattern (which determines theshape of the contact opening 208) is different when processing theinterlayer insulating film 207 by dry etching. All other points arecommon.

Third Embodiment

A structure of an insulated gate field-effect semiconductor deviceaccording to a third embodiment is described by referring to FIG. 16 andFIG. 17. FIG. 16 is a plane sectional view, and a longitudinal sectionalview at position C-C thereof is FIG. 17. FIG. 16 is a sectional view oflevel A-A in FIG. 17. A sectional view of position B-B in FIG. 16 andFIG. 17 is same as FIG. 1 relating to the first embodiment except thatthe reference numerals 1** are changed to 3**. A sectional view ofposition D-D in FIG. 16 is same as FIG. 3 relating to the firstembodiment except that the reference numerals are changed similarly. Inthe following explanation of the embodiment, when referring to FIG. 1and FIG. 3, it is supposed that the reference numerals are changed insuch manner.

In the insulated gate field-effect semiconductor device of theembodiment, what differs from the insulated gate field-effectsemiconductor device of the first embodiment lies only in the impurityconcentration in the semiconductor region at four corners of the contactopening 308. The shape of the contact opening 308 itself is arectangular shape same as in the prior art. Other parts are common withthe insulated gate field-effect semiconductor device in the firstembodiment. The common points are quoted from the description of thefirst embodiment, and only the different point is explained.

In the insulated gate field-effect semiconductor device of thisembodiment, the plane shape of the P+ emitter region 300 is differentfrom that of the first and second embodiments. More specifically, inthis embodiment, the P+ emitter region 300 is not formed at four cornersof the contact opening 308. In these portions, a P field region 311 withlower impurity concentration than in the P+ emitter region 300 contactswith the emitter electrode 309. Thus, same as in the first and secondembodiments, there is an advantage that harm by concentration of holecurrent after switching off is less. This is because the P field region311 is lower in impurity concentration as compared with the P+ emitterregion 300 and is hence higher in resistance. Accordingly, part of holecurrent from the P field region 211 to the emitter electrode 209 afterswitching off tends to once leave the P field region 311 to the P+emitter region 300 of lower resistance and escape from there into theemitter electrode 309, rather than escaping directly into the emitterelectrode 309 from the P field region 311 of high resistance.Accordingly, the peak value of the local current density at the apicesof four corners of the contact opening 308 is lower than in the priorart.

Area of the contact opening 308 is not changed from that of therectangular contact opening 908 (FIG. 19) of the prior art. To thecontrary, since a part is occupied by the P field region 311 of highresistance, the total resistance is slightly higher. Hence, in ON state,holes do not escape to the emitter electrode 309 too much. Hence, the ONvoltage is low.

In the insulated gate transistor of the embodiment, the shape of thecontact opening 308 may be formed of curved lines at four corners asshown in the first embodiment. In this variation, the feature of thisembodiment and the feature of the first embodiment are both realized.Therefore, current concentration is lessened more favorably. Of course,same as in the first embodiment, the four corners may be formed byobtuse angles and straight lines, or the four corners may be formed bymerely rounding. Or the shape of the contact opening 308 may be extendedin the width in both end portions as shown in the second embodiment. Inthis variation, the feature of this embodiment and the feature of thesecond embodiment are both realized. Therefore, current concentration islessened more favorably. Of course, all of the features of thisembodiment, of the first embodiment, and of the second embodiment may berealized in one variation. Even if such measure is taken only atterminal ends of the device array, a certain effect is expected.

Manufacturing process of insulated gate transistor of the embodiment issimilar to manufacturing process of insulated gate transistor of thefirst embodiment except that only the mask pattern (which determines theshape of the contact opening 208) is different when processing theinterlayer insulating film 307 by dry etching, and that the mask patternis different in ion implantation for forming P+ emitter region 300. Allother points are common.

As specifically described herein, in the foregoing embodiments, theinsulated gate transistors divided by the P field region, having theemitter, body, and collector, and controlling conduction between emitterand collector by voltage applied to the gate electrode, have at leastone of the features (1) to (3) below. (1) The shape of the contactopening where the emitter region and the emitter electrode contact isformed in curved lines or obtuse angle at four corners. This eliminatesright-angle apex. (2) The shape of the contact opening is basically arectangular shape, formed in a wider shape in the both end portions thanin the central portion. (3) The impurity concentration in thesemiconductor region at four corners of the contact opening is lowerthan the impurity concentration in other parts than the four corners.

Accordingly, without increasing the ON voltage in ON state, localconcentration of hole current into the emitter electrode from the fieldregion after switching off is lessened. In particular, it is significantin the terminal end of the device array. Thus, the contradictoryproblems of low ON voltage and prevention of excessive heat generationafter switching off are both solved.

The foregoing embodiments are mere examples, and are not intended tolimit the invention what so ever. Therefore, the invention may bechanged or modified freely within a range not departing from the truespirit thereof. For example, in the central portion of the contactopening 108 (the reference numeral in the first embodiment is citedherein, but it is same in other embodiments), the specific configurationof the N+ emitter region 104 and P+ emitter region 100 is not limited tothe example shown in FIG. 2. It may be stripe type parallel or verticalto the gate electrode 106, ladder type, dot type, etc. The plane shapeof the gate electrode 106 is not limited to rectangular shape, but mayinclude polygonal, circular, elliptical or other shape. Accordingly, thecontact opening 108 is not limited to stripe shape, but may be formed indot shape. The structure of the gate electrode 106 includes, aside fromthe trench type, planar type, concave type and others. The material ofthe gate electrode 106 is not limited to N semiconductor, but mayinclude P semiconductor or metals.

As for the internal structure of the semiconductor substrate, variousmodifications may be considered. For example, the impurity concentrationin the N drift region 102 is not required to be uniform. It may be alsoformed as punch-through type forming an N+ buffer region of highconcentration between the N drift region 102 and P+ collector region101. Or it may be also formed as collector short type having the N driftregion 102 or N+ buffer region partly short-circuited with the collectorelectrode 110. The type of the semiconductor device is not limited tothe insulated gate transistor alone. For example, MOS control thyristoror diode may be used.

The conductive type (P type and N type) of the semiconductor regions maybe exchanged. The semiconductor itself may be other than silicon (SiC,GaN, GaAs, etc.). The insulating film (gate insulating film 105,interlayer insulating film 107) is not limited to an oxide film, but anitride film or composite film may be also used.

INDUSTRIAL APPLICABILITY

As clear from the description herein, the invention presents asemiconductor device lessened in current concentration at the corner ofin the contact opening after switching off without heightening the ONvoltage. As a result, suppressing local heat generation after switchingoff, a stable operation is realized at large current.

1. A semiconductor device comprising: an emitter region provided in asemiconductor substrate facing its principal plane, a body regionprovided below the emitter region, a drift region provided below thebody region, a gate electrode of trench structure, insulated from eachof the emitter region, the body region, and the drift region, a fieldregion provided in the semiconductor substrate facing its principalplane, the field region being configured to divide the emitter regionand the body region into cells, and a contact electrode provided outsideof the semiconductor substrate connecting with the emitter region andthe field region, wherein the emitter region, the body region, and thedrift region constitute an insulated gate transistor divided by thefield region, the field region is the same conductive type as a portionof the emitter region that contacts with the field region, the fieldregion being low in impurity concentration, the field region contactswith the contact electrode at a corner portion of contacting portion ofthe semiconductor substrate to the contact electrode, and the emitterregion contacts with the contact electrode at another portion than thecontacting portion of the field region to the contact electrode withinthe contacting portion of the semiconductor substrate to the contactelectrode.
 2. A semiconductor device of claim 1, wherein a plurality ofinsulated gate transistors are discretely arranged in the semiconductorsubstrate, and each insulated gate transistor has a contacting portionto a contact electrode, and a corner portion of a contacting portion ofan insulated gate transistor positioned at the end and at opposite sideto another insulated gate transistor is formed with a curved line orwith an obtuse angle.
 3. A semiconductor device of claim 1, wherein theshape of contacting portion of the insulated gate transistor to thecontact electrode is formed in a broader width in an end portion than inthe central portion.
 4. A semiconductor device of claim 3, wherein aplurality of insulated gate transistors are discretely arranged in thesemiconductor substrate, and each insulated gate transistor has acontacting portion to a contact electrode, an end portion of acontacting portion of an insulated gate transistor positioned at an endand at opposite side of another insulated gate transistor is formedbroader than the central portion of the contacting portion, and a cornerportion of the end portion is formed with a curved line or with anobtuse angle.
 5. A semiconductor device comprising: an emitter regionprovided in a semiconductor substrate facing its principal plane, a bodyregion provided below the emitter region, a drift region provided belowthe body region, a gate electrode of trench structure, insulated fromeach of the emitter region, the body region, and the drift region, afield region provided in the semiconductor substrate facing itsprinciple plane, the field region being configured to divide the emitterregion and the body region into cells, and a contact electrode providedoutside of the semiconductor substrate conducting with the emitterregion, the contact electrode having a corner portion, wherein theemitter region, the body region, and the drift region constitute aninsulated gate transistor divided by the field region, the field regionis the same conductive type as a portion of the emitter region thatcontacts with the field region, the field region being low in impurityconcentration, and a corner portion of a contacting portion of theemitter region mating with the corner portion of the contact electrodehas an impurity concentration that is lower at the corner portion of thecontacting portion than in other portions of the contacting portion. 6.A semiconductor device of claim 5, wherein a plurality of insulated gatetransistors are discretely arranged in the semiconductor substrate, andeach insulated gate transistor has a contacting portion to a contactelectrode, and a corner portion of a contacting portion of an insulatedgate transistor positioned at an end and at opposite side of anotherinsulated gate transistor is lower in impurity concentration than otherportion of the contacting portion.